The present invention relates generally to non-volatile semiconductor memory devices and, more specifically, to a method of sensing data stored in a memory cell of a flash memory device.
A semiconductor memory device can be roughly classified as either a volatile semiconductor memory device or a non-volatile semiconductor memory device. Volatile semiconductor memory devices can be classified as dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices. Volatile semiconductor memory devices have rapid read/write speeds but, unfortunately, the contents stored therein disappear when external power is cut off.
Non-volatile semiconductor memory devices can be classified as mask read-only memory (MROM) devices, programmable read-only memory (PROM) devices, erasable programmable read-only memory (EPROM) devices, or electrically erasable programmable read-only memory (EEPROM) devices. Non-volatile semiconductor memory devices hold their contents even when external power supply thereto is interrupted. Non-volatile semiconductor memory devices are therefore used to store contents that must be maintained even in the event of power loss.
In MROM, PROM, and EPROM devices, however, it is inconvenient to erase and write data, and general users therefore have difficulty updating the stored contents therein. Data stored in EEPROM devices, on the other hand, can be electrically programmed and erased quickly, and the use of these devices has therefore become popular in auxiliary memory and system programming devices that require continuous updating of contents. Furthermore, large-volume auxiliary memory devices typically use flash EEPROM devices because they have a higher integration density than conventional EEPROM devices. Among the various types of flash EEPROM devices, the integration density of NAND-type devices is generally higher than NOR- and AND-type devices.
A flash EEPROM device includes memory cells, each of which includes a floating gate transistor having a source, a drain, a floating gate, and a control gate. A memory cell in a NAND-type flash EEPROM device is electrically erased and programmed using Fowler-Nordheim (F-N) tunneling current. Various methods for erasing and programming NAND-type flash EEPROM devices are disclosed in U.S. Pat. No. 5,473,563, entitled xe2x80x9cNonvolatile Semiconductor Memoryxe2x80x9d, and in U.S. Pat. No. 5,696,717, entitled xe2x80x9cNonvolatile Integrated Circuit Memory Devices Having Adjustable Erase/Program Threshold Voltage Verification Capabilityxe2x80x9d, the disclosures of which are incorporated herein by reference.
In general, an erased memory cell (ON cell) stores data of a logic xe2x80x9c1xe2x80x9d. When a read voltage of 0V is applied to a word line coupled with the erased memory cell, current flows through the ON cell. A programmed memory cell (OFF cell) stores data of a logic xe2x80x9c0xe2x80x9d. When a read voltage of 0V is applied to a word line coupled with the programmed memory cell, no current flows through the OFF cell.
FIG. 1 is a schematic circuit diagram of a conventional non-volatile semiconductor memory device, according to the prior art. As illustrated in FIG. 1, bit lines BL1 to BL4 are arranged in communication with a memory cell array 10. For clarity of description, only four bit lines BL1 to BL4, and their related page buffers, are illustrated in FIG. 1. The bit lines BL1 to BL4 are arranged in pairs BL1 and BL2, BL3 and BL4 with each bit line pair connected to a corresponding sense node SO1, SO2 through a respective bit line bias and select section 12_O, 12_E of the page buffer. A corresponding precharge section and a sense and latch section 14_O, 14_E is also connected to a respective one of the sense nodes SO1, SO2.
More specifically, an odd bit line bias and select section 12_O selects a bit line of the first bit line pair BL1 and BL2. An even bit line bias and select section 12_E selects a bit line of the second bit line pair BL3 and BL4. Each of the bit line bias and select sections 12_O and 12_E includes four NMOS transistors M1 to M4, connected as illustrated. Selected bit lines are connected with corresponding sense nodes SO1 and SO2, and unselected bit lines are fixed at a predetermined voltage (e.g., 0V). The precharge section of each page buffer includes a PMOS transistor M6. Each of the sense and latch sections 14_O, 14_E includes three NMOS transistors M5, M7, M8 and a latch formed from two inverters INV1, INV2.
FIG. 2 is a timing diagram illustrating an operation of one of the page buffers of the conventional memory device of FIG. 1. Referring to FIGS. 1 and 2, odd-numbered bit lines BL1, BL3 and even-numbered bit lines BL2, BL4 are selected by different page addresses, and a read operation is carried out in a page unit. When memory cells connected to bit lines of an even-numbered page address are accessed, memory cells connected to bit lines of an odd-numbered page address are shielded (and vice-versa).
Shielding unselected bit lines is done to prevent parasitic coupling capacitance between adjacent bit lines, which increases as a bit line pitch is reduced. If bit lines adjacent to selected bit lines are not shielded, then when a bit line connected to an ON cell is discharged, a voltage on a bit line connected to an OFF cell that is being floated may be coupled down together with the ON cell. When this happens, the OFF cell may be improperly recognized as an ON cell, thereby resulting in a read error.
Assuming, for example, that the even-numbered bit lines BL2, BL4 are selected based on an even-numbered page address, the odd-numbered bit lines BL1, BL3 are shielded by applying a ground voltage (0V) through the NMOS transistors M1. In this case, during a precharge period, a power supply voltage Vcc is supplied to the sense nodes SO1, SO2 through the PMOS transistors M6. The PMOS transistors M6 each have a gate that receives a precharge control signal nSOSHLD. At this time, the selected bit lines BL2, BL4 are precharged with a precharge voltage Vpre through the fourth NMOS transistors M4, which are controlled by an even bias control signal BLBIAS_E. Unselected bit lines BL1, BL3 are floated because the third NMOS transistors M3 are turned off by an odd bias control signal BLBIAS_O.
After the selected bit lines BL2, BL4 are charged up to the precharge voltage Vpre, a voltage on the even bias control signal BLBIAS_E is changed from the precharge voltage Vpre to a ground voltage GND, so that the fourth NMOS transistor M4 of each bias and select section is turned off. The even bit lines BL2, BL4 are then floated, while the sense nodes SO1, SO2 are maintained at a high voltage level Vcc. When the selected bit lines BL2, BL4 are floated, voltages of those bit lines BL2, BL4 vary depending on states of corresponding cell transistors.
For example, assuming that an ON cell is connected to the second bit line BL2 and an OFF cell is connected to the fourth bit line BL4, the second bit line BL2 voltage is gradually reduced as cell current flows through the ON cell. The fourth bit line BL4 voltage, however, is maintained at the precharge voltage Vpre because the corresponding OFF cell prevents current flow. During this xe2x80x9cbit line develop period,xe2x80x9d since the precharge control signal nSOSHLD is at a low level, each PMOS transistor M6 becomes active, and each sense node SO1, SO2 is thereby maintained at a high voltage level Vcc.
After voltages of the selected bit lines BL2, BL4 have been developed, the even bias control signal BLBIAS_E has a sense voltage level Vsen that is lower than the precharge voltage level Vpre. This causes the fourth NMOS transistor M4, coupled with the second bit line (corresponding to an ON cell), to be turned on. The fifth NMOS transistor M5, coupled with the fourth bit line (corresponding to an OFF cell), is turned off.
Before a voltage of the even bias control signal BLBIAS_E is increased up to the sense voltage Vsen, the precharge control signal nSOSHLD transitions from low to high, thereby floating the sense nodes SO1, SO2. As a result, a voltage on the first sense node SO1 is rapidly lowered toward a bit line level through a discharge path that consists of the fourth NMOS transistor M4 of the odd bit line bias and select section 12_O, the second bit line BL2, and the ON cell transistor. On the other hand, since the fourth NMOS transistor M4 of the even bit line bias and select section 12_E, coupled with the bit line BL4, is turned off, the second sense node SO2 is maintained at a high voltage level Vcc.
A threshold voltage of a sixth NMOS transistor M7 is higher than the precharge voltage Vpre. For this reason, the sixth NMOS transistor M7, having a gate connected to the first sense node SO1, is turned off, while the sixth NMOS transistor M7, having a gate connected to the second sense node SO2, is turned on. When a latch signal xcfx86LATCH is activated to its high level, a value Q1 of a latch (including two inverters INV1, INV2) of the sense and latch section 14_O is maintained at an initial value (e.g., xe2x80x9c0xe2x80x9d). A value Q2 of a latch (including two inverters INV1, INV2) of the sense and latch section 14_E becomes high (e.g., xe2x80x9c1xe2x80x9d). This period is called xe2x80x9ca sense period.xe2x80x9d
A read operation of the non-volatile semiconductor memory device according to the prior art has several disadvantages. Among other things, a sense node (e.g. SO2) corresponding to an OFF cell is floated during the sense period, because its corresponding fourth NMOS transistor M4 and PMOS transistor M6 are all turned off. Accordingly, when a voltage of an adjacent sense node (e.g. SO1), corresponding to an ON cell, falls toward a bit line level, a voltage of the adjacent floated sense node is affected by parasitic coupling capacitance Cc between the sense nodes. Referring to FIG. 3A, if the parasitic coupling capacitance Cc is small, the effect of that capacitance Cc on the floated sense node SO2 may be insufficient to lower the voltage of the floated sense node SO2 below a high voltage Vcc level.
However, as a design rule is reduced, integration density is increased and the distance between bit lines is reduced. Parasitic coupling capacitance Cc is therefore inevitably increased. Referring to FIG. 3B, a voltage of the floated sense node SO2 may therefore be coupled down based on voltage variations of the adjacent sense node SO1. The greater the influence by an adjacent sense node SO1 on a floated sense node SO2, the more the voltage of the floated sense node SO2 will be lowered. If the floated sense node voltage is lowered below a trip voltage Vtrip for changing a latch value of a page buffer, a read error occurs.
As illustrated in FIG. 3B, for example, a latch value Q2 has an erroneous data value of xe2x80x9c0xe2x80x9d rather than the expected value of xe2x80x9c1xe2x80x9d because of the coupling down of the floated sense node SO2 due to parasitic capacitance with the adjacent sense node SO1. Therefore, although an integration density increases, a read scheme is required to prevent the voltage of a floated sense node from being affected by neighboring sense nodes.
An object of this invention is to enable a non-volatile semiconductor memory device capable of reducing read errors that result from capacitive coupling between adjacent sense nodes.
Another object of the present invention is to provide a read method capable of reducing read errors caused by capacitive coupling between adjacent sense nodes.
Still another object of the present invention is to provide a non-volatile semiconductor memory device having a sensing structure suitable for high-density integration.
According to a first aspect of the present invention, a method of sensing data stored in an array of memory cells arranged at intersections of rows and columns is provided. According to this method, a precharge voltage is supplied to the columns. The precharge voltage is then cut off to develop voltages of the columns. A sense voltage is supplied to first columns to sense voltages on first sense nodes during a first sensing period. Also during the first sensing period, second sense nodes, corresponding to second columns, are supplied with a predetermined bias voltage.
In accordance with another aspect of the present invention, a memory device includes an array of memory cells arranged in rows and columns. A page buffer circuit has page buffers corresponding to the columns. Each of the page buffers includes a bias transistor connected between a corresponding column and a sense node, a current supplying transistor connected between a power supply voltage and the sense node, and a latch connected to the sense node. A method of reading data from this memory device begins by supplying a precharge voltage to the columns and then cutting off the precharge voltage to develop voltages of the columns. A sense voltage is then supplied to first columns to sense voltages on first sense nodes corresponding to the first columns during a first sensing period. During the first sensing period, the first sense nodes are connected to or floated from the even-numbered columns based on a state of the respective memory cells. The second sense nodes, corresponding to second columns, are supplied with a predetermined bias voltage.
In accordance with still other aspect of the present invention, a non-volatile memory device includes an array of memory cells arranged in rows and columns. A plurality of page buffers are connected to the columns. Each of the page buffers comprises a bias transistor connected between a corresponding column and a corresponding sense node, a latch connected to the corresponding sense node, and a precharge transistor connected between a power supply voltage and the corresponding sense node. A control logic controls the page buffers during a read mode of operation. In this embodiment, the control logic controls the bias and precharge transistors of the respective page buffers so that second sense nodes are fixed at a predetermined bias voltage during a first sensing period while voltages on first sense nodes are sensed. The control logic controls the bias and precharge transistors of the respective page buffers so that the first sense nodes are fixed at the predetermined bias voltage during a second sensing period when voltages on the second sense nodes are sensed.